1. Field of The Invention
The present invention relates to a technique for synthesizing control logic and mapping it in an efficient manner, and particularly to condensing and storing control signals corresponding to reachable states for driving a reconfigurable piece of logic hardware so as to minimize control logic circuitry.
2. State of The Art
Digital circuits are often designed with a control model having a logic hardware block 1 for performing a specific function and a control logic block 2 for generating control signals for driving the logic hardware block as shown in FIG. 1A.
The control logic block 2 is often implemented using logic gates, programmable logic arrays (PLAs), gate arrays, standard cells, and/or field programmable gate arrays (FPGAs) for implementing a specific logical function in order to generate the set of control signals. The internal logic within the control logic block 2 of the control model may be derived, compiled, or synthesized from a user""s input description/statements which define the function that the control model is to perform. A user""s input description may comprise a hardware description language such as Verilog code or a higher lever programming language such as the C programming language, or may comprise any other description language used to describe the control model shown in FIG. 1A.
The control logic block 2 provides N control signals from a set of registers (R1, R2, R3, RN) each having contents determined by a given function implemented by the control logic within the control block. For instance, as shown in FIG. 1A, control signal 1 is provided by register R1 which is determined by a function f1. Similarly, driving signal 2 is provided by register R2 which is determined by a function f2. The functions (e.g., f1, f2, etc.) are embodied within the control logic block as logic gates and registers so as to create a finite state machine (FSM) where the current state is dependent on previous state conditions. In a simplified example, if f1=A AND B, then the function f1 might be embodied as an AND gate having its inputs coupled to input signals A and B and its output coupled to register R1. In general, the more complex the function is, the more logic circuitry is required. Commonly in this type of system, condition codes and f1ag signals generated in the logic hardware block 1 are fed back to the control logic block 2 as inputs.
FIG. 1B shows an example of a system for performing logic circuit synthesis which compiles the user""s input description of the function to be performed for the control model shown in FIG. 1A. In one such logic synthesis system (described in U.S. Pat. No. 5,970,254, assigned to the assignee of the present application, and incorporated herewith), the user input description 3 is synthesized by synthesis tool 8 to generate configuration information 9 which, in this example, is stored into hard disc memory 10. The synthesis system also includes a Reconfigurable Logic Hardware Fabric 4 having a reconfigurable control path 5, a reconfigurable datapath 6, and a reconfigurable memory path 7, each having an associated configuration memories 12A-12C, respectively. Configuration bit streams 11 are loaded from the memory 10 into configuration memories 12A-12C for configuring each of the control path, datapath and memory path to synthesize the logic function as described in the original user input description.
The user input description 3, or the corresponding configuration information synthesized therefrom, may define boolean logic statements and conditions to be implemented by the control path 5 of the Reconfigurable Logic Hardware Fabric 4. For instance, a given set of control signals a, b, c, can be expressed in a logic function statement within the input description as follows: (a AND b) OR c. The configuration bits synthesized from the user description defining this logic function are used to configure the control path 5 which, in turn, performs the logic function and generates control signals 10A for coupling to the datapath 7. The datapath 7 is made up of a plurality of logic circuits (not shown) which are designed to perform a plurality of functions dependent on the configuration bit stream provided from its corresponding configuration memory 12 and dependent on the control signals provided from control path 5. For instance, each logic circuit (also referred to as a datapath unit (DPU)) can perform any type of boolean function as well as multiplexing, decrementation, and incrementation. One exemplary embodiment of a DPU is described in U.S. patent application Ser. No. 09/307,072, filed May 7, 1999 and incorporated herewith.
In a similar manner, control block 5 provides control signals to memory path 6 for controlling memory read and write operations, dependent on the synthesized input description.
Hence, the synthesis system shown in FIG. 1B utilizes the control model as shown in FIG. 1A. Specifically, a control logic block (e.g., control path 5) provides a set of control signals to a logic hardware block (e.g., either/or both of datapath 7 and memory path 6) dependent on the user input description.
The present invention is a system and method of efficiently providing control or driving signals from a control logic block to a piece of logic hardware by condensing and mapping control logic block functions to a look-up table thereby minimizing control logic circuitry. This system and method of providing control are particularly adaptable to a logic synthesis system having reconfigurable control and datapath circuitry such as described above.
A system having a control structure which includes a look-up table which stores reachable states of control signals and a method thereof of implementing the system is described. An input description is provided by a system user to define the behavior of the function to be implemented by the system. The system includes a control logic block configured to provide a M-bit control signal address to access a look-up table storing the reachable states of a N-bit control signal for driving a logic hardware block, where M less than  less than N.
In accordance with the method of implementing the above system, initially, the input description is synthesized to generate an implementation description of the system. The implementation description describes the system in terms of a control model having a control model control logic block which drives a control model logic hardware block with N control signals. The implementation description is analyzed to determine the reachable states of the N control signals (i.e., the different possible combinations of the N-bit control signal dependent on the functions defined by implementation description). A look-up table is created in such that each entry of the look-up table stores a N-bit control word corresponding to each reachable state of the N control signals. Each entry in the look-up table represents configuration information for driving the logic hardware block to perform functions as defined by the input description. Next, a control logic block is configured or programmed by 1) determining a mapping function between the reachable states of the N-bit control signal to a M-bit address for accessing each look-up table entry wherein each reachable state as defined by the original N driving signals is mapped to a different address and 2) by implementing the mapping function in the control logic block. In one embodiment, the mapping function can be implemented by programming a programmable logic array (e.g., PLA), or any other similar programmable device. In another embodiment, the mapping function is implemented by determining configuration bits for programming a reconfigurable control logic block to perform the mapping function. Once the control structure is established by configuring the control logic block and creating the reachable state look-up table, the control logic block (configured by the predetermined configuration bits) implements the mapping function between the reachable states and the look-up table addresses and generates a M-bit address for accessing a N-bit reachable state control word in the look-up table. The logic hardware block is then driven by the accessed N-bit control word and performs its function as defined by the input description.
In an alternative embodiment, the system and method of control is employed in a reconfigurable logic synthesis system having a reconfigurable logic hardware fabric which includes at least a reconfigurable control path and reconfigurable datapath where the datapath includes a plurality of programmable datapath units (DPUs). A user input description defines the function to be synthesized by the reconfigurable logic hardware fabric. The reconfigurable control path is configured to output M-bit control signal addresses, each for accessing a different reachable state look-up tablexe2x80x94one per DPU in the datapath. Each of the accessed reachable state look-up tables outputs a N-bit control signal for driving its corresponding DPU.
In the embodiment of the method of implementing the reconfigurable system, the user input description is initially synthesized to generate an implementation description of the system. The implementation description describes the system in terms of a control model having a control model control path which drives a control model datapath with N control signals and in terms of the hardware elements which are to be implemented by the datapath of the system. The implementation description is analyzed to identify the hardware elements called out within the implementation description so as to group and assign them in an efficient manner into specific DPUs. In addition, the implementation description is analyzed to determine the reachable states of the N control signals for driving each of the DPUs. A look-up table, referred to as a configuration storage memory (CSM), is created for each DPU in which each entry in the CSM stores a N-bit control word corresponding to one of the determined reachable states for each DPU. Each entry in the CSM table represents control or configuration information for driving the grouped hardware elements within the DPU to perform functions as originally designated in the user description. Next, the reconfigurable control path is configured by 1) determining for each set of CSM and its corresponding DPU the mapping function between the reachable states of the N-bit driving signal associated with the grouped hardware elements in the DPU and a M-bit control word address for accessing the DPU""s corresponding CSM and 2) determining configuration/programming bits for programming or configuring the control path to implement each of the mapping functions. Once the control structure is established by configuring the control logic block and creating the CSM for each DPU, the control path and datapath simulate a logic circuit as defined by the input description.